1. Field of the Invention
The present invention relates generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating an interconnect structure in an integrated circuit.
2. Description of the Prior Art
As integrated circuits become more and more complex, the need for increased packaging density, reduced device parasitics, and low resistivity interconnects increases. Buried contacts and self-aligned contact techniques have been developed to increase packaging density. Similarly, silicides are utilized to reduce device parasitics as well as interconnect resistances.
One method known in the art to form a silicided interconnect utilizes a refractory metal, such as titanium, and amorphous silicon. A patterned layer of amorphous silicon is formed over a layer of refractory metal, and the integrated circuit is then annealed to form silicide. The silicide creates the interconnect structure. Those skilled in the art will recognize that during silicidation a monocrystalline silicon, such as a semiconductor substrate, is consumed faster than amorphous silicon. Furthermore, because the amorphous silicon layer is typically consumed during the silicidation process, a thicker silicided layer is formed in the area covered with the amorphous silicon layer than in the areas not covered with the amorphous silicon layer.
This difference between the silicidation rates of amorphous silicon and a monocrystalline silicon such as a semiconductor substrate can lead to problems with the integrated circuit. Forming a thick silicided area utilizing amorphous silicon over a source/drain region within a semiconductor substrate can cause dopants in the source/drain regions to out-diffuse through the silicide to other areas and reduce the effective junction concentration, resulting in junction leakage. This phenomena is due to the fact that the monocrystalline silicon in the semiconductor substrate is consumed faster than the amorphous silicon during the silicidation process. Those skilled in the art will recognize that losing the silicon in the source/drain regions during silicidation and having dopants out-diffuse into other areas can lead to the problem of junction leakage.
Therefore, it would be desirable to provide a method to form interconnect structures which limits the thickness of the interconnect structure, minimizes diffusion of dopants, and which reduces the potential for junction leakage. It is also desirable that such a method not significantly increase the complexity of the fabrication process.